发明名称 |
Method of correcting single errors |
摘要 |
Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit positions. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.
|
申请公布号 |
US5631915(A) |
申请公布日期 |
1997.05.20 |
申请号 |
US19950468277 |
申请日期 |
1995.06.06 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MEANEY, PATRICK J.;CHEN, CHIN-LONG |
分类号 |
G06F11/10;H03M13/13;(IPC1-7):H03M13/00 |
主分类号 |
G06F11/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|