发明名称 |
Method for preventing multi-level cache system deadlock in a multi-processor system |
摘要 |
A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.
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申请公布号 |
US5632025(A) |
申请公布日期 |
1997.05.20 |
申请号 |
US19960696788 |
申请日期 |
1996.08.14 |
申请人 |
SILICON GRAPHICS, INC. |
发明人 |
BRATT, JOSEPH P.;BRENNAN, JOHN;HSU, PETER Y. T.;HUFFMAN, WILLIAM A.;SCANLON, JOSEPH T.;CIAVAGLIA, STEVE |
分类号 |
G06F12/08;(IPC1-7):G06F12/14 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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