| 摘要 |
PROBLEM TO BE SOLVED: To provide clear timing to data and to attain sampling of data by configuring an SAR chip so as to work in the 1st or 2nd mode corresponding to two data speeds respectively and interfacing the chip with a PHY chip or the like. SOLUTION: A 40Mhz clock signal MCLK is generated for a 1st mode of a data speed 622Mbps of an SAR chip 10. Data to be sent to a PHY chip 18 receives a timing from the SAR chip synchronously with a rising of the MCLK and gives an inverted TCXLK to the PHY chip. The PHY chip samples data at the rising of the TCLK according to a UTOPIA protocol. With respect to the 2nd mode of data speed 155Mbps, the 40Mhz MCLK of the SAR is converted into a couple of 20MHz. The timing of the data sent to the PHY is taken only at selection rising time according to the protocol and the data are sampled by the PHY. The data received by the SAR are synchronized again next or merged with the MCLK. |
