INTER-CLOCK DELAY GENERATING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To suppress the generation of noise including a high frequency component by reducing the high level period of a system clock about to a half when power supply voltage is high and to obtain an operation margin by increasing the high level period of the system clock when the power supply voltage is low. SOLUTION: A multi-phase clock groupϕn-1,ϕn,ϕn+1 is generated by inputting a signal CL(τ) generated by delaying a reference clock CL by prescribed time to a multi-phase clock generating circuit 7. An inter-clock delay is generated by an output signal from a two-input AND circuit 17 for inputting the output signal of a two-input NAND circuit 16 for inputting the reference clock CL and the signal CL(τ) and the n-th clockϕn in the multi-phase clock group.