| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of address signal lines of a decoder circuit, reduce the occupancy area of a driving circuit, and reduce the cross talk between lines by selectively driving the signal lines of a matrix via the combination of multi-phase clock signals and the decoder circuit. SOLUTION: Four-phase clocks are divided into eight-phase clocks by a frequency dividing circuit 101 and fed to a decoder 103. The reference clock signal and the clock signal phase-shifted from it by 180 deg. are fed to a synchronization counter circuit 102, these clock signals are frequency-divided, and multiple signals are outputted. These signals are fed to a decoder 103 to select signal lines. The outputs of the decoder 103 are the logical products of the eight-phase clock signals and the outputs of the synchronization counter 102, and the signal lines connected to the outputs are selected when they are all turned on. An increase of the occupancy area caused by an increase of the number of lines is prevented. |
