| 摘要 |
<p>PROBLEM TO BE SOLVED: To prepare the main signal train of a bit array in a correct order by adjusting reception side clocks so as to be synchronized with transmission side clocks in the serial-parallel/parallel-serial conversion of transmission signals. SOLUTION: In a high-speed signal system, there is provided with a serial- parallel conversion part 1 for performing conversion from serial to parallel main signals. A phase monitoring part 6 for monitoring the approaching conditions of the phases of the transmission side clocks and the reception side clocks is provided, the phase of the reception side clocks is adjusted by the approached signal output 68 and third clocks 71 are prepared. By the adjusted third clocks 71, parallel main signals 53 are converted to the serial main signals 54 of the bit array in the correct order and outputted.</p> |
