发明名称 REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE AND ITS REDUNDANCY DECODER
摘要 <p>PROBLEM TO BE SOLVED: To provide a redundant circuit which can quickly select a redundant word line in a synchronizing type semiconductor memory. SOLUTION: This device is provided with an address buffer 14 outputting a redundant address RAi making an input address XAi synchronized with a first synchronizing signal KFRST, a redundant decoder 15 having a program means programming an address ands actively outputting a redundant decoding signal RPi synchronizing with a second synchronizing signal KFRST 2 when the programmed address coincides with the redundant address RAi, and a redundant word line decoder 16 selecting a redundant work line in accordance with the redundant decoding signal RPi. As the signal RPi is synchronized with the synchronized signal KFRST 2, a delay time of the redundant decoder can be shortened without considering active and non-active margin of the signal RPi.</p>
申请公布号 JPH09128993(A) 申请公布日期 1997.05.16
申请号 JP19960224143 申请日期 1996.08.26
申请人 SAMSUNG ELECTRON CO LTD 发明人 KEN EKISHIYU;CHIYOU TETSUMIN
分类号 G11C11/413;G11C11/401;G11C11/407;G11C11/408;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 主分类号 G11C11/413
代理机构 代理人
主权项
地址
您可能感兴趣的专利