| 摘要 |
PROBLEM TO BE SOLVED: To reduce bit line resistance and simplify a manufacturing processes. SOLUTION: N<+> impurity diffusion layers 3 and a gate electrode 5 are formed on the main surface of a P-type semiconductor substrate 1. An insulating layer 6 and interlayer insulating layers 7a, 7b are formed so as to cover the gate electrode 5. A wiring layer 10 is formed on the interlayer insulating layer 7a, and a through hole 10a is formed in the wiring layer 10. A contact hole 8b is formed in the interlayer insulating layer 7a, and pillar-shaped parts 9b are formed in the contact hole 8b and the through hole 10a. A bit line 11 is formed by using the pillar-shaped parts 9b and the wiring layer 10. |
