| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a memory test system provided with a pattern generator capable of performing accurate multiple bit tests in any cases and to improve fault coverage. SOLUTION: This system is provided with the pattern generator 11 provided with an address generation means 21 for supplying addresses to a memory 13 to be tested, data generation means 22, 23 and 26 for supplying write data to the memory 13 to be tested, a clock generation means 24 for supplying control clocks to the memory 13 to be tested, the control means 25 and a logic circuit 41 for outputting the expectation data of the complementary logic of the write data in response to control signals MBT and compares read data from the memory 13 to be tested with the expectation data ED by a logic comparator 15. Even though there is a case that accurate defect judgement can not be performed when the write data to the memory 13 to be tested and the expectation data ED of a comparison object logically match in the multiple bit tests, by providing the logic circuit 41, the logic of both is made opposite in such a case and the accurate defect judgement is performed.</p> |
