| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a data output buffer for a memory for high frequency which can output stable data with low power consumption and at high speed and can also suppress a power source noise. SOLUTION: A first driving section 36 generates a pull-up control signal DOK of a Vcc level when a data line DB is transferred to HIGH. A duration detecting section 38 generates a level shift control signal when HIGH continues for a delay time or more in the data line DB. A level shifter 40 generates a level shift signal LTS of a Vpp level in accordance with a level shift control signal. A booster circuit 44 performs boosting operation responding to a signal LTS, and generates a signal DOK of the Vpp level. When the data line DB is transited at high speed for a period shorter than a delay time of the duration detecting section 38, an output terminal Dout is made a first output level of Vcc-Vtn by the signal DOK of the Vcc level. When the data line DB is transited at low speed for a period longer than a delay time of the duration detecting section 38, an output terminal Dout is made a second output level of Vcc by the signal DOK of the Vpp level of the booster circuit 44.</p> |
