| 摘要 |
PROBLEM TO BE SOLVED: To provide a method in which a test pattern used to activate a predesignated path is generated easily and in which an inactive path is detected easily and to provide a delay verification method which utilizes the method. SOLUTION: In a method, logic circuit description information 101, element delay information 102, path designation information 103 and designation latch information 112 are input, and a test pattern 111 which activates a predesignated path is generated. In the method, the output value of an element is set, an input value is decided on the basis of the output value of the element, whether an inconsistency exists or not is investigated, and the test pattern which activates the designated path is generated. |
