Arrangement for parallel data communications between data processor and bus controller

摘要

The arrangement exchanges data elements of data packets between the data processor (3) and the bus controller (4) using a multiple access technique. Each packet whose length exceeds the width of the data bus is broken up into data bus wide data elements which are passed sequentially. The division of the packets and the number of access steps per multiple access are adapted to minimise the difference from the next packet exceeding the data bus width. The interface device (46) sets a multiple access in the next buffer stage each time an access is made to a data element following the last data element of the current data packet.