发明名称 |
Numerisches Steuerungssystem unter Einsatz eines Personalcomputers und Verfahren zum Steuern desselben |
摘要 |
A PLL circuit 31 of a pulse convert/output circuit 12 in an NC board A 1 receives a fundamental clock signal CLK through a PC extension bus 207 from a fundamental clock generating circuit 201, and generates a sync pulse signal PLS on the basis of the received fundamental clock signal CLK. The sync pulse signal PLS is inputted to a gate 34. A signal select circuit 33 receives an address signal AD, or a RESET signal or an IRQ signal through the PC extension bus 207, and generates a pulse-outputting permission signal N3 on the basis of the received signal. The pulse-outputting permission signal N3 controls a gate 34 which determines the timing of starting the outputting of the sync pulse signal PLS. Consequently, a sync signal PLSOUT that is synchronized with those in the remaining NC boards is generated. |
申请公布号 |
DE19645735(A1) |
申请公布日期 |
1997.05.15 |
申请号 |
DE1996145735 |
申请日期 |
1996.11.06 |
申请人 |
MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP |
发明人 |
FUJISHIMA, MITSUSHIRO, TOKIO/TOKYO, JP |
分类号 |
G05B19/05;G05B19/18;G05B19/414;G05B19/418;G06F1/04;G06F11/00;G06F11/32;(IPC1-7):G05B19/414;G06F17/50;G06F13/12 |
主分类号 |
G05B19/05 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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