| 摘要 |
PCT No. PCT/US96/17130 Sec. 371 Date Apr. 16, 1998 Sec. 102(e) Date Apr. 16, 1998 PCT Filed Oct. 24, 1996 PCT Pub. No. WO97/15929 PCT Pub. Date May 1, 1997A NAND stack array (95') is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state. |
