Two-dimensional associative processor and data transfer method

摘要

A two-dimensional PE (processing element) array that can achieve a small amount of hardware, short transfer time and high flexibility. It includes q x r CAMs (11), where q and r are any integers equal to or greater than two, and hit-flag lines (16). Each CAM (11) has one-dimensionally arrayed w words (24), a hit-flag register (27) capable of shift up and shift down, and an upper shift I/O port (26) and a lower shift I/O port (29) for inputting from and outputting to outside the contents of the hit-flag register (27). Each of the hit-flag lines (16) connects the lower-shift I/O port (29) of one of two horizontally adjacent CAMs (11) with the upper-shift I/O port (26) of the other of the two. The w words (24) are arranged in m rows and n columns and are connected in a zigzag, and each word (24) is assigned to a PE that performs various types of logical and arithmetic operations. <IMAGE>