发明名称 |
CMOS transistor network to gate level model extractor for simulation, verification and test generation |
摘要 |
A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles all CMOS logic families including static, precharge, pass CMOS switching network and self-resetting families. The output gate level model can be used in variety of applications including but not limited to logic simulation, verification, test generation, debug, diagnosis, etc.
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申请公布号 |
US5629858(A) |
申请公布日期 |
1997.05.13 |
申请号 |
US19950406283 |
申请日期 |
1995.03.17 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KUNDU, SANDIP;KUEHLMANN, ANDREAS;SRINIVASAN, ARVIND |
分类号 |
G01R31/3183;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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