| 摘要 |
A method and apparatus is disclosed for an analog-to-digital converter (ADC) to minimize power consumption. The ADC of the present invention minimizes the number of clock cycles required to determine the correct digital code for a particular sample point on an electrogram signal, thus making it possible to turn off some or all of the ADC logic during idle periods. The ADC includes prediction logic that provides a starting point for subsequent digital code representations of the electrogram signal. The prediction logic receives recent code conversions values to predict a current digital code value. This predicted digital code is converted to an analog value and compared with the actual electrogram signal. Next, the ADC adds (or subtracts) a constant value (C) to (or from) the predicted code and compares the result to the electrogram signal. If the ADC determines that the predicted value is within the constant value (C) of the correct digital code, then the ADC counts in the proper direction until the comparator changes output state. If the ADC determines that the predicted value is not within the constant value (C), then the successive approximation logic is enabled and used to find the correct code. |
