发明名称 |
Methods and systems for merging data during cache checking and write-back cycles for memory reads and writes |
摘要 |
Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.
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申请公布号 |
US5627993(A) |
申请公布日期 |
1997.05.06 |
申请号 |
US19960639398 |
申请日期 |
1996.04.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ABATO, RICHARD P.;GREER, WILLIAM R.;HERRING, CHRISTOPHER M. |
分类号 |
G06F12/08;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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