Display buffer using minimum number of VRAMs

摘要

A display buffer includes a plurality of memory banks, each said bank having a plurality of ordered rows of data storage locations. Circuitry controls the storage of a plurality of sequenced lines of display data in said display buffer. A first set of lines of display data is stored at contiguous locations in a first memory bank with the first word of a first line being stored in a location offset from the first location of the first row so a last word of a last line is stored in the last location of the last row. A second set of lines is stored at contiguous locations starting at the first row of the second memory bank. A last line of the second set of lines is stored so that the last word of this last line is stored in the last location of a selected row of the second bank. A third set of lines is stored in a third memory bank starting at a memory line other than the first memory line. If additional space is needed, the display lines wrap around to the first location of the first line of the third bank of memories. A graphics processor may provide the memory addressing and bank selection logic.