SYNCHRONOUS SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To shorten a sum of a cycle time and a clock access time and reduce a count of circuits, namely, an area of a chip, by constituting a register circuit of an output part of one latch circuit and a pulse generator generating pulses synchronous with a clock controlling the latch circuit. SOLUTION: A pulse generation circuit PG generates pulses of a pulse width tp delayed by a delay time td from an external clock signal CLK. When the width tp and the time td and suitably set, fresh data D(An ) can be brought on a data bus DB while a pulse signal CLKP is low. Consequently, a latch circuit F3 of an output part having the pulse signal CLKP input to a control input terminal C is turned to a through state while the pulse is generated. The data D(An ) are accordingly transmitted to an output buffer OB without a wait time and output to an external output terminal Out. If the pulse width tp is set to be a suitable length, the data on the data bus DB are never switched to next data during the generation of pulses and therefore, the output part carries out a registering operation.