发明名称 |
Improved device planarity |
摘要 |
A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely. <IMAGE> |
申请公布号 |
EP0704893(A3) |
申请公布日期 |
1997.05.02 |
申请号 |
EP19950114889 |
申请日期 |
1995.09.21 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
JAIN, MANOJ KUMAR;CHISHOLM, MICHAEL FRANCIS |
分类号 |
H01L21/3205;H01L21/304;H01L21/3105;H01L21/768;H01L23/528;H01L29/34;(IPC1-7):H01L21/768;H01L21/310 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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