| 摘要 |
<p>PROBLEM TO BE SOLVED: To easily cope with various circuit speeds in a simple constitution and also to reduce the hardware scale. SOLUTION: An ATN cell switch part 1A outputs a cell synchronizing clock SWCLK, an output cell, an output cell synchronizing signal SWSYNC and a stop synchronizing signal STOPSYNC and also receives the stop signal from a circuit corresponding part L1. Furthermore, the part 1A applies the signal STOPSYNC to the part L1 and also receives a stop signal from the part L1 to control the output speed of the output cell. Thus the part 1A can reduce the FIFO capacity of the part L1.</p> |
