High-speed ISA bus control system for changing command cycle execution speed by selectively using ISA bus controller and high-speed bus controller

摘要

A system controller is provided with an ISA bus controller that executes a command cycle at a speed complying with the standards for ISA buses and a high-speed bus controller that executes a command cycle at a higher speed. When an I/O device that can operate at higher speeds than that of the ISA bus for a PCMCIA controller and IDE interface, a high-speed bus controller is used in place of the ISA bus controller. The high-speed bus controller executes a command cycle at a speed corresponding to the performance of the addressed I/O device. When a busy signal (an inactive IORDY signal) indicating that data transfer is not in time is outputted from the I/O device side, the cycle width of the command is lengthened. There are a synchronous sampling mode and an asynchronous sampling mode for the IORDY signal. The cycle from when IORDY goes off until the command goes off is set in a programmable manner.