Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge

摘要

An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.