| 摘要 |
A step-form wave generating circuit is provided which is constructed in such a manner that output data Q3 among data Q1-Q5 outputted from flip-flops FF1-FF4 serially connected is directly outputted as data X3 through an inverter I6, the remaining data is outputted as data X1, X2, X4 and X5 through transfer gates (T1,T2),(T3,T4),(T5,T6),(T7,T8) to which a clock pulse CK8 divided by eight is directly applied or applied through an inverter I1, the voltage of the contact point of the common output port of N-type current mirrors N1-N4 changed by the data X1-X4 and resistor RN is applied to the input port of a buffer B1 through an NMOS NM5 which is turned on during a half a period of the input data X5, and the voltage of the contact point of the common output port of P-type current mirrors P1-P4 changed according to input data and resistor RP is applied to the input port of the buffer B1 through an NMOS NM4 which is turned on during a half a period of the input data X5.
|
