| 摘要 |
The TV chrominance signal detecting circuit comprises a plurality of exclusive OR gates(11,13) to which 2's compensation type of I, Q signals are inputted; adders(12,12', 14,14') in which the outputs of the exclusive OR gates(11,13) are added; AND gates(15,16) for applying carry inputs to the adders(12',14'); latches(17,18) for latching the outputs of the adders(12,12' and 14),14'); latches(21,22) for latching the output of I2 and Q2 ROM(19) to I2 and Q2 signals; an adder(24) in which the outputs of the latches(21,22) are added; a LOG ROM(25) in which the output of the adder(24) is log-processed; a multiplier(26) in which the output of the Log ROM(25) is 1/2 multiplied; an ANTI LOG ROM(27) in which the output of the multiplier(26) is ANTI log-processed to output the result as a signal size; a LOG ROM(20) in which the outputs of the adders(12,12') is log-processed; a subtracter(23) in which the output of multiplier(26) and the output of the Log ROM(20) are subtracted; ARC COS ROM(28) ANT LOG ROM(29) in which the Log A/1 output of the subtracter(23) is ARC COS-processed and ANTI log-processed to output .THETA.; and delay circuit(31,32).
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