发明名称 DATA PROCESSING SYSTEM COMPRISING AN ASYNCHRONOUSLY CONTROLLED PIPELINE
摘要 A data processing system transports data via successive stages of a pipeline. Whenever possible the stages are in the transparent mode so that data made available can travel through the pipeline with a minimum delay. The arrival of data is signaled by a preceding stage by making the potential on a conductive connection to the stage high. In response thereto the stage switches over to a hold mode which enables new data to be made available on its input even before the data has been passed on. The stage makes the potential on the conductive connection to the next stage high and the potential on the conductive connection to the preceding stage low again, and also sets a register. The register is reset and the stage becomes transparent again as soon as it receives an acknowledge signal from its successor, signifying that the data has been taken up. For as long as the register is in the set state, the stage does not respond to the fact that the potential on the connection to the preceding stage becomes high, except that the stage itself starts to keep the potential on the connection high. 00000
申请公布号 WO9708620(A3) 申请公布日期 1997.04.24
申请号 WO1996IB00811 申请日期 1996.08.16
申请人 PHILIPS ELECTRONICS N.V.;PHILIPS NORDEN AB 发明人 VAN BERKEL, CORNELIS, HERMANUS
分类号 G06F13/42;G06F5/06;G06F9/38;G06F12/08 主分类号 G06F13/42
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