| 摘要 |
Speed, robustness and static performance of TSPC (True Single Phase Clocking) latches and flipflops are analysed in this paper. New latches and flipflops are proposed to upgrade the overall speed, power saving, clock slope insensitivity and static performance of TSPC. Both new single-rail and new dual-rail latches and flipflops are proposed. Among them are different dynamic, semi-static and fully-static versions. The delays are reduced by factors of 1.3, 2.1, 2.2 and 2.4 for the single-rail dynamic, the dual-rail dynamic, the semi-static and the fully-static versions respectively. In the same time, power consumptions are also reduced so the power-delay products are reduced by factors of 1.9, 3.5, 3.4 and 6.5 respectively for an average activity rate (0.25). These improvements are accompanied with less transistor counts and less clock loads. One unique type of the proposed latches uses only a single clocked transistor and only n-transistors in logic (in both n- and p-latches and in both dynamic and static versions). |
