Durch Ereigniss befähigte Prüfarchitektur für integrierte Schaltungen

摘要

A boundary test architecture for use in an integrated circuit (10) comprises input and output test registers (12, 22) having functions controlled by a event qualifying module (EQM) (30). The EQM (30) receives a signal from the output test register (22) indicating that a matching condition has been met. In response to a matching condition, EQM (30) may control the input and output test on the incoming and outgoing data. During testing, tests on the incoming and outgoing data. During testing the internal logic (20) may continue to operate at-speed, thereby allowing the test circuitry to detect faults which would not otherwise be discoverable. A memory buffer (64) may be included to store a plurality of input data for test data.