发明名称 Integrated circuit with planarized dielectric layer between successive polysilicon layers
摘要 <p>A method of forming a portion of a semiconductor integrated circuit having a semiconductor substrate as well as the resulting integrated circuit. In the inventive method, various steps are involved. In one embodiment, for example, the method steps are as follows. First, there is formed a first polysilicon layer overlying and in contact with the semiconductor substrate. Second, a plurality of conductive members are patterned from the first polysilicon layer. Third, there is formed a dielectric layer having an upper planar surface and having a lower surface contacting the semiconductor substrate and the plurality of conductive members from the first polysilicon layer. Fourth, there is formed a second polysilicon layer overlying and in contact with the dielectric layer. Fifth, a plurality of conductive members are formed from the second polysilicon layer. Lastly, there is formed a metallic layer over the plurality of conductive members from the second polysilicon layer. &lt;IMAGE&gt;</p>
申请公布号 EP0769813(A2) 申请公布日期 1997.04.23
申请号 EP19960307356 申请日期 1996.10.09
申请人 STMICROELECTRONICS, INC. 发明人 LIN, YIH-SHUNG
分类号 H01L21/768;H01L21/8244;H01L27/11;(IPC1-7):H01L21/768 主分类号 H01L21/768
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