| 摘要 |
PROBLEM TO BE SOLVED: To supervise a bit phase at all times by starting bit phase synchronization as soon as a latch clock and a transfer clock are received. SOLUTION: The bit phase synchronization circuit is made up of an input stage latch means 10 to latch input data DIN, a frequency divider means 20 applying 1/2 frequency division to a 1st clock CK1 , a phase comparator means 30 comparing a phase of a frequency division clock obtained by the 1/2 frequency divider means 20 with a phase of a 2nd clock CK2 , and a phase adjustment means 40 to transfer the input data DIN at a clock with an optimum phase based on the result of comparison by the phase comparator means 30. The 1st clock CK1 and the input data DIN are given to the latch means 10. The phase adjustment means 40 transfers the input data DIN from the 1st clock CK1 to the 2nd clock CK2 without double reading or missing of data based on the result of detection by the phase comparator means 30. |
