发明名称 METHOD FOR SHORTENING AND REDUCING TEST SET
摘要 PROBLEM TO BE SOLVED: To discriminate the disturbance to vector shortening and test cycle reduction of a generated test sequence, specify the unspecified bit of the partially specified test sequence by a sliding anchor frame technique, generate the following sequence for removing the disturbance, and improve the test speed. SOLUTION: Together with the progress of generation of test sequences, the bottle neck disturbing the vector shortening and test cycle reduction to a generated test sequence is discriminated. Then, intending to remove the bottle neck of the previously generated test sequence, the subsequent test sequence is generated. In a sliding anchor frame technique used for this bottle neck removing frame work, each vector of the partially specified test sequence is taken into consideration as anchor vector during the extension of the sequence. Thus, a minimum test set can be generated, and used together with all combinational circuits.
申请公布号 JPH09105770(A) 申请公布日期 1997.04.22
申请号 JP19960246631 申请日期 1996.09.18
申请人 NEC CORP 发明人 SHIYURIMATSUTO CHIYAKURATSUDA;ANANDO RAGUNASAN
分类号 G01R31/28;G01R31/3183;G06F11/22 主分类号 G01R31/28
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