| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL which outputs a clock signal or the like stably locked to an input reference signal regardless of the variance of the input reference signal. SOLUTION: The PLL circuit consists of a phase comparator 1, a VCO 3, a clock generator 4, and a counter s to obtain an output signal S3. The clock generator 4 has the frequency division rate set by the value of a parameter PX. An output signal S4 of an LPF 2 and a certain voltage S5 are compared with each other by a comparator 6, and a phase delay signal S6 is outputted when the signal S4 is higher than the voltage S5. The frequency in occurrence is calculated in accordance with this signal S6 by a phase deviation calculation part 8c of an MPU 8 provided with a clock function 8b; and if this frequency exceeds a certain value, the deviation from the frequency range where the clock is stably outputted by the parameter PX is decided, and the parameter in the center of parameters for lock and output of the current frequency in the phase delay direction is selected from parameters in a parameter table 8e by a parameter selection part 8d and is set to the clock generator 4. |
