| 摘要 |
<p>PROBLEM TO BE SOLVED: To decrease the layout area of memory while suppressing stress developed in program operation by applying a specified voltage to a bit line or word line thereby lessening the withstand voltage element. SOLUTION: When a data stored in a page buffer is 1, a first voltage of about 4.5V, higher than the power supply voltage Vcc, is applied to a bit line BL and a second voltage of about 6V is applied to an SSL connected with the gate of a string select transistor ST. After the first voltage is transmitted to the source of ST, transition is made to the first voltage for the SSL thus breaking the ST. Subsequently, a third voltage of 8-11V is applied to a nonselected word line WL and a program voltage is applied simultaneously to a select WL. In this regard, the voltage being applied to a memory cell is set at such level as causing no F-N tunneling phenomenon in order to prevent programming of a selected memory cell. This arrangement simplifies isolation between bit lines or page suffers while eliminating an anti-programming voltage generation circuit.</p> |
