MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To form a wiring part and a connection hole easily, by flattening a step part between a memory array and a peripheral circuit in a DRAM with a structure of a stacked capacitor. SOLUTION: First layers of wirings 18A and 18B are formed on a BPSG film 17 that covers an upper electrode 16 in a capacitive element (C) used for data accumulation. In this case, wirings 18A and 18B are formed only in a peripheral circuit and not in a memory array. As a result, when a silicon oxide film 19 is etched back and flattened, the quantity of etch back is increased for the silicon oxide film 19 as a high step part in the memory array.