| 摘要 |
PROBLEM TO BE SOLVED: To avoid resistance increase of an interconnection which connects a gate electrode to a source or drain diffusion layer by forming a polycrystalline Si layer on the marginal inner wall of each of openings to cover an oxide film after forming a diffused layer and removing the oxide film remaining at the opening to increase the area of the diffused layer beneath the oxide film. SOLUTION: On a semiconductor substrate 1 an oxide film 2 and polycrystalline Si layer 3 are formed, part of this layer 3 is processed to form openings to expose that layer 2 and impurity is implanted into the substrate 1 to form a polycrystalline Si layer 6 on the inner wall of each opening 4. A second conductivity type impurity is ion-implanted into the substrate 1 through the layer 2 exposed in the openings to form a diffused layer 5. Then the film 2 exposed in the openings is etched off to increase the area of the layer 5 beneath the film 2 around the openings 4, this facilitating the etching at forming of the gate interconnection. Thus, the increase of the resistance of the interconnection which connects the gate electrode to the source or drain diffused layer can be suppressed. |
