STRUCTURE AND METHOD FOR SIGNED MULTIPLICATION USING LARGE MULTIPLIER HAVING TWO EMBEDDED SIGNED MULTIPLERS

摘要

A signed multiplier circuit (200) performs selectable multiplication operations on a first word having an upper byte and a lower byte and a second word having an upper byte and a lower byte. A first multiplier means (231, 232) generates a first product representative of the product of the upper bytes of the first and second words plus the product of the lower bytes of the first and second words. A second multiplier means (230, 233) generates a second product representative of the product of the upper byte of the first word and the lower byte of the second word plus the product of the lower byte of the first word and the upper byte of the second word. The second multiplier means (230, 233) can be selectively disabled. When the second multiplier means (230, 233) is enabled, the multiplier circuit (200) multiplies the first and second words. When the second multiplier means (230, 233) is disabled, the multiplier circuit (200) multiplies the upper bytes of the first and second words and the lower bytes of the first and second words.