GATABLE LEVEL-PULLING CIRCUIT

摘要

Integrated circuit components automatically establish or disable a level-pulling condition relative to a given input IC pin (22) as a function of detected signal activity at such IC pin. A logic signal responsive to signal activity at the IC pin drives the gate (32a) of a field effect transistor (FET 32) to dynamically establish or disable level-pulling function at the IC pin. Alternative embodiments include a flip-flop register (40) and an OR gate (60, Fig. 3) driving the gate of the FET.