发明名称 SRAM STORAGE CELL
摘要 A three-transistor SRAM memory cell includes a bistable field-effect transistor having a fully depleted floating channel region and a hysteretic gate voltage characteristic curve. The bistable field-effect transistor has a gate to be connected to a first bit line for the purpose of writing to the memory cell and a second channel terminal to be connected to a second bit line for the purpose of reading from the memory cell. The two bit lines can be identical. The connection between the bit lines and the bistable transistor can be effected through first and second respective transistors which are each controlled by a respective word line.
申请公布号 WO9711465(A3) 申请公布日期 1997.04.17
申请号 WO1996DE01745 申请日期 1996.09.16
申请人 SIEMENS AKTIENGESELLSCHAFT;GOSSNER, HARALD;EISELE, IGNAZ;WITTMANN, FRANZ;RAMGOPAL RAO, VALIPE 发明人 GOSSNER, HARALD;EISELE, IGNAZ;WITTMANN, FRANZ;RAMGOPAL RAO, VALIPE
分类号 G11C11/412;G11C11/40;G11C16/04 主分类号 G11C11/412
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