摘要 |
<p>A data round-off device is provided in which a digital input signal of m-bit form (m is an integer) which has arithmetically been processed by addition, subtraction, multiplication, and division by an orthogonal transformer or predictive encoder is summed, if it is positive, with a value of 2<(n-1)>-1 (n is a natural number smaller than m) and if negative, with a value of 2<(n-1)> and the higher (m-n) bits of a resultant sum signal are delivered as the output of the data round-off device. Preferably, it is used for control of the number of bits if there is a difference in the number of bits between the data output of an orthogonal transformer and the data input of an encoder for encoding the data output of the orthogonal transformer. <IMAGE></p> |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA, OSAKA, JP |
发明人 |
TATSURO, JURI, MIYAKOJIMA-KU, OSAKASHI, OSAKA-FU 534, JP;SHINYA, KADONO, KATANO-SHI, OSAKA-FU 576, JP |