Method and circuit for rearranging output data in variable-length decoder

摘要

There is provided a method and a circuit (10) for rearranging output data in a VLD. The circuit (10) for rearranging output data in a VLD has an internal memory (15), a first data processor (11) for packing a variable-length decoded bit stream in a packed data unit having a predetermined number of bits, generating a write address for each packed data unit to store the packed data unit in the internal memory (15), and generating a request signal for transmitting the stored packed data to an external memory, when the number of packed data units stored in the internal memory (15) exceeds a predetermined threshold value, and a second data processor (13) for generating respective read addresses for reading out N packed data units from the internal memory (15), when an accept signal is generated in response to the request signal, and applying the generated read address to the internal memory (15). Therefore, a timing margin can be ensured through request and accept, an automatic byte-alignment by start code is possible. Further, writing and reading timing of a memory is stabilized, and write and read banks of the memory is efficiently switched during writing and reading operations.