| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve efficiency of the space by constituting a signal processing circuit for hierarchical encoding/decoding and a memory as a one-chip IC, to prevent the increase of memory capacity for storing the data of respective hierarchies and further, to unnecessitate a picture element delay circuit and a line delay circuit excepting for the memory. SOLUTION: The 1st hierarchical (input image) data are successively written in a memory 1a. Data stored in a memory 1b are read out and added with input pixel data, the added output is written in the same address, and the data of the 2nd hierarchy (the average value of data of the 1st hierarchy) are stored in the memory 1b. Data stored in a memory 1c are read out, the output adding the data selected by a selector 4d and the read data is written in the same address, and the data of the 3rd hierarchy (the average value of data of the 2nd hierarchy) are stored in the memory 1c.</p> |
