Data processor with unified store queue permitting hit under miss memory accesses

摘要

A store queue for use in a data processor (10) with a memory storage system has a first-in-first-out ("FIFO") queue (48) and control circuitry (52). The control circuitry maintains three pointers which index the entries in the FIFO queue: a dispatch pointer (D), a completion pointer (C), and an oldest miss pointer (OM). The control circuitry stores each stole instruction in the entry designated by the dispatch pointer and then increments the dispatch pointer. The control circuitry increments the completion pointer when the data processor indicates that the previously designated store instruction is the oldest instruction in the data processor: when the instruction is "completed." The control circuitry increments the oldest miss pointer after it presents the previously designated store instruction to the memory system.