Variable-length decoding apparatus using relative address

摘要

A variable-length decoding apparatus outputs symbol data corresponding to variable-length data. The data may be presented in units of a block having a predetermined magnitude. The apparatus has a memory composed of a plurality of storage regions for outputting information. Each storage region is designated by an absolute address. Each storage region contains relative address data, symbol data and a status signal representing whether or not a symbol is determined and indicative of the class of the determined symbol. The apparatus also has an absolute address generator for generating absolute address data in response to a control signal and the relative address data supplied from the memory, as well as a controller for generating the control signal in response to a start signal indicative of a start of each block having a predetermined magnitude, and the status signal supplied from the memory. The controller may also form the control signal dependent upon the initial bit of variable-length-coded data in a block. Thus, the control circuit can be designed in hardware without using a barrel shifter, and a variable-length decoding table can be embodied by using a memory having a small capacity.