Receiver clock recovery method for constant bit rate digital signal in ATM network

摘要

The method involves using receiver side cell storage using FIFO memory, whose level is held at approximately half full in the middle by controlling the read-out clock frequency. The actual middle value of the level is computed for each time interval with its deviation from the half full state of the FIFO memory. Correction values are derived from the computed values and added to the control parameter. Up and down count comparisons of write and read clocks are used for monitoring the achieved level. An adder for adding a correction value to the detected level is inserted before the memory. The correction value is generated by a programmable component from the offset between the half full and achieved levels.