| 摘要 |
<p>A communication receiver (100) utilizing a synthesizer (143) employs a discrete-time phase locked loop which includes a reference oscillator (135), a phase error detector (202), a discrete-time analog computing element (206), an integrator (210), a controlled frequency generator (211, 212), and a frequency divider (214). The discrete-time analog computing element implements a discrete-time analog lead-lag network circuit. This circuit includes a clock and logic circuit (216), at least one discrete-time analog queuing element (218), and an analog computing engine (222). The queuing element (218) includes N analog signal lines, N analog storage lines, N control lines, and N2 controllable switches. Each controllable switch is coupled between each of the N analog signal lines and each of the N analog storage lines. In addition, N charge storage elements are coupled between each of the N analog storage lines and a common circuit node. The N control lines control the controllable switches in a predetermined sequence.</p> |
