ATM SWITCH WITH VC PRIORITY BUFFERS

摘要

An ATM switch (10) has a plurality of link controllers (12) each having a FIFO (30) for each VC established and a FIFO (32) for each priority level. Cells are pushed into the VC FIFO (30) and a pointer to the VC FIFO (30) is pushed into an arbitration FIFO (32) for the priority level of the VC FIFO (30). The arbitration FIFOs (32) are examined according to a schedule and cells are popped up from VC FIFOs (30) according to priority for exit from the controller (12). According to one embodiment, the highest priority arbitration FIFO (32a) is always examined first and none of the lower priority arbitration FIFOs (32b-32d) are examined unless the highest priority arbitration FIFO is empty. According to another embodiment, timers are set for the lower priority arbitration FIFOs (32b-32d) and if a timer expires for a lower priority arbitration FIFO, it is examined.