A current memory has an input (1) which is connected via a switch (S1) to inputs of a coarse memory cell (CM) and a fine memory cell (FM). On a phase phi 1 of a clock signal the switch (S1) closes. During a first part phi 1a of the clock phi 1 of the coarse memory cell samples the input current and the outputs the sampled current thereafter. During a second part phi 1b of the clock phi 1 the fine memory cells senses and stores the difference between the input current and the output current of the coarse memory (CM). An output switch (S5) closes on phase phi 2 of the clock, thereby passing the combined outputs of the coarse and fine memories to an output (2). A resistor rs is provided between the common nodes of the coarse and fine memories, having a resistance equal to the "on" resistance of the output switch (S5). This substantially compensates for the voltage drop caused by the internal resistance of the output switch in the closed state, thereby reducing current transport error between the coarse and fine memories.
