发明名称 METHOD AND SYSTEM FOR GENERATING TEST PATTERN FOR LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a test pattern generation system in which the logical state can be set at a plurality of points in a logic circuit by inserting a circuit, producing a specified output when a plurality of nodes are in specified logic states, additionally into the logic circuit. SOLUTION: An input section 101 inputs a circuit data, a plurality of nodes to be controlled, and the circuit information, e.g. the logical state at each node, to a pseudo circuit generating section 140 and the information is read in at a read-in section 141. The node to be branched is then extracted from the circuit information and a circuit, producing a specified output when a plurality of nodes take specified logic states, is inserted additionally into the logic circuit. The additional circuit is a single output element having a plurality of nodes to be controlled simultaneously as the inputs and the output thereof is led out to an external output terminal. When a plurality of nodes are collected at one output (node), a test pattern can be generated for a single node. When the output from the inserted element is led out to an external terminal, useless signal propagation path can be eliminated.
申请公布号 JPH0996664(A) 申请公布日期 1997.04.08
申请号 JP19950253623 申请日期 1995.09.29
申请人 TOSHIBA CORP 发明人 IWASA TOMOE
分类号 G01R31/3183;G06F11/22 主分类号 G01R31/3183
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