发明名称 |
Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms |
摘要 |
A processor providing a redundant intermediate form of a result in fewer than the total number of clock cycles needed to calculate a final complete result. The redundant form is forwarded to subsequent instructions or operations capable of utilizing the redundant intermediate form to enhance the performance of the processor.
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申请公布号 |
US5619664(A) |
申请公布日期 |
1997.04.08 |
申请号 |
US19950402322 |
申请日期 |
1995.03.10 |
申请人 |
INTEL CORPORATION |
发明人 |
GLEW, ANDREW F. |
分类号 |
G06F9/302;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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